AMD recently announced the general availability of the world’s first data center CPU using 3D die stacking, the 3rd Gen AMD EPYC™ processors with AMD 3D V-Cache™ technology, formerly codenamed “Milan-X.” Built on the “Zen 3” core architecture, these processors expand the 3rd Gen EPYC CPU family and can deliver up to 66 percent performance uplift across a variety of targeted technical computing workloads versus comparable, non-stacked 3rd Gen AMD EPYC processors.
These new processors feature the industry’s largest L3 cache, delivering the same socket, software compatibility and modern security features as 3rd Gen EPYC CPUs while providing outstanding performance for technical computing workloads such as computational fluid dynamics (CFD), finite element analysis (FEA), electronic design automation (EDA) and structural analysis. These workloads are critical design tools for companies that must model the complexities of the physical world to create simulations that test and validate engineering designs for some of the world’s most innovate products.
“Building upon our momentum in the data center as well as our history of industry-firsts, 3rd Gen AMD EPYC processors with AMD 3D V-Cache technology showcase our leadership design and packaging technology enabling us to offer the industry’s first workload-tailored server processor with 3D die stacking technology,” said Dan McNamara, senior vice president and general manager, Server Business Unit, AMD. “Our latest processors with AMD 3D V-Cache technology provide breakthrough performance for mission-critical technical computing workloads leading to better designed products and faster time to market.”
“Customers’ increased adoption of data-rich applications requires a new approach to data center infrastructure. Micron and AMD share a vision of delivering full capability of leading DDR5 memory to high-performance data center platforms,” said Raj Hazra, senior vice president and general manager of the Compute and Networking Business Unit at Micron. “Our deep collaboration with AMD includes readying AMD platforms for Micron's latest DDR5 solutions as well as bringing 3rd Gen AMD EPYC processors with AMD 3D V-Cache technology into our own data centers, where we are already seeing up to a 40% performance improvement over 3rd Gen AMD EPYC processors without AMD 3D V-Cache on select EDA workloads.”
AMD started with Zen3 cores, the foundation of the best-performing processors on the market, 3rd Gen EPYC. AMD tripled the L3 cache available on existing 3rd Gen EPYC processors, bringing the total to a massive 768 MB per socket or 1.5 GB per 2P server. With Milan as foundation, AMD is maintaining compatibility with SP3 systems. A BIOS upgrade is all that’s needed to enable existing Milan servers to support Milan- X, but customers still get the security, IO bandwidth, and compatibility benefits of Milan.
Designed for Specific Workloads
AMD is bringing four Milan-X SKUs to the market. Each one represents unique value for particular workloads. An “X” at the end of the model number indicates that the part features AMD 3D V-Cache. Every Milan-X model has 8 Core Complex Dies or CCDs, each of which contains 96 MB of L3 cache, for a total of 768MB. And the Zen 3 shared L3 cache model means that any single core can access the full 96 MB.
These processors were engineered to work within the power and thermal design specifications of existing Milan high frequency parts so that customers would have the flexibility to choose high frequency Milan or large cache Milan-X in the same server platform with the same number of memory and I/O channels. Milan-X is a premium product, but the average increase in price is just 20% over the equivalent Milan high frequency part.
3rd Gen AMD EPYC Processors with AMD 3D V-Cache technology help technical computing workloads scale across on-premise clusters and bring HPC- level performance to the datacenter for time-sensitive projects.
Performance Benefits
EDA is the core of the semiconductor industry. And RTL Simulation makes up the majority of the work in digital circuit simulation.
The 16 core Milan-X processor accelerates RTL Simulation by 66% over the fastest 16 core Milan part. To put that into context, the expected performance uplift for EDA tools is 8-12% per generation. If you recall that Milan-X is still based on Milan – the same Zen3 compute cores, with a massive L3 cache – then you’ll understand how significant this is to the semiconductor market. Customers who have already qualified on Milan can upgrade in place to Milan-X with no change to their applications and experience an immediate uplift.
Workloads that may be a fit for Milan-X
Workloads that likely won’t benefit from Milan-X
3rd Gen EPYC with 3D V-Cache: Designed for Technical Computing
AMD EPYC 7003 Series processors are already the world’s highest performing for general-purpose computing. With the addition of AMD 3D V-Cache™ technology, EPYC processors reach new heights to become the world’s highest performing x86 server processors for technical computing—designed to accelerate product development cycles and boost productivity.
As a design target for Milan-X, we zeroed in on technical computing applications. These are some of the most complex and demanding workloads in the data center.
These applications are typically enablers of product design.
These tools are used to simulate and improve the design of physical systems. Just as these software solutions are used to simulate the physical world around us, EDA tools are used to simulate and optimize chip design. While architecting Milan-X, AMD looked deeply into how these applications behave and found that a large cache was critical to attaining better performance. More L3 cache ensures that critical data is closer to the cores and that reduces latency in the system.
With this new innovation, AMD will continue to deliver a new level of performance to their large customer base globally.
